Microprocessors and in particular microcontrollers, use interrupt controllers to manage a plurality of possible interrupt sources and program exception handling. Interrupts generally request an exception in the sequential processing of a program. If this interrupt request is handled, the execution of an interrupt service routine (ISR) will occur. An ISR allows the program to properly handle the respective interrupt source, thus removing the interrupt's request. However, entering and exiting the respective ISR requires context saving and restoring. Context saving and restoring will be referred to as any operations preformed by the program to ensure that the microprocessor returns to the sequential processing of the program in the same state as it was before an interrupt request occurred. This context saving and restoring will also be referred to as interrupt latency, and will be measured as a unit of time starting from the time the first operation of context saving or restoring occurs and ends when the last operation of context saving and restoring occurs. ISR content saving will be referred to as preamble and context restoring will be referred to as post-amble. In particular, preamble may include a register set associated with the central processing unit (CPU) of the microprocessor or microcontroller. A register set or register file is generally used in combination with an arithmetic logic unit (ALU) of the CPU to perform arithmetic and/or logic as well as data/address moving operations on data or addresses stored in these registers. Thus, even though, generally, such a register set is considered to be part of the CPU, for purposes of this application the term register set or register file may be used separately from the term CPU. However, no limitation is to be inferred from the way these terms are used. A register set can be within or outside a CPU.
The preamble or post-amble of the ISR can have varying degrees of latency. Hence, high frequency interrupt requests with high ISR latency can consume significant processor time
In order to reduce ISR latency, microprocessors or microcontrollers may have a separate register set for ISRs which is referred to as a shadow register set. For example, the 32-bit microcontroller PIC32MX3XX/4XX manufactured by Microchip have a processor core that automatically switches to a shadow register set whenever the highest assignable interrupt priority is serviced. However, this known system is not flexible and may be difficult to be adapted for controlling systems that manage multiple interrupt sources. Hence, a more flexible system is needed.